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| STV850 CY2SSTV850 Differential Clock Buffer/Driver Features * Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications * 1:10 differential outputs * External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input * SSCG: Spread AwareTM for EMI reduction * 48-pin SSOP and TSSOP packages * Conforms to JEDEC JC40 and JC42.5 DDR specifications Description This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels. This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA. The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks. Block Diagram Pin Configuration 10 YT0 YC0 YT1 YC1 YT2 YC2 SCLK SDATA Serial Interface Logic YT4 YC4 YT5 YC5 YT6 YC6 CLKINT CLKINC PLL FBINT FBINC YT7 YC7 YT8 YC8 YT9 YC9 CY2SSTV850 YT3 YC3 AVDD FBOUTT FBOUTC VSS YC0 YT0 VDDQ YT1 YC1 VSS VSS YC2 YT2 VDD SCLK CLKINT CLKINC VDDI AVDD AVSS VSS YC3 YT3 VDDQ YT4 YC4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS YC5 YT5 VDDQ YT6 YC6 VSS VSS YC7 YT7 VDDQ SDATA FBINT FBINC VDDQ FBOUTC FBOUTT VSS YC8 YT8 VDDQ YT9 YC9 VSS Cypress Semiconductor Corporation Document #: 38-07457 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 18, 2001 CY2SSTV850 Pin Description[1, 2] Pin 13 14 35 36 3, 5, 10, 20, 22 46, 44, 39, 29,27 2, 6, 9, 19, 23 47, 43, 40,30,26 32 Name CLKINT CLKINC FBINC FBINT YT(0:9) YC(0:9) FBOUTT I/O I I I I O O O Description Complementary Clock Input. Complementary Clock Input. Feedback Clock Input. Connect to FBOUTC for accessing the PLL. Feedback Clock Input. Connect to FBOUTT for accessing the PLL. Clock Outputs Clock Outputs Feedback Clock Output. Connect to FBINT for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Feedback Clock Output. Connect to FBINC for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Serial Clock Input. Clocks data at SDATA into the internal register. Data Input for the two-line serial bus Data Input and Output for the two-line serial bus Differential Outputs Differential Outputs Differential Input Electrical Characteristics LV Differential Input 33 FBOUTC O 12 37 SCLK SDATA I, PU I/O, PU Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 2.5V power Supply for Logic 11 4, 21, 28, 34, 38, 45 16 15 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 17 VDD VDDQ AVDD VDDI VSS AVSS 2.5V Nominal 2.5V Power Supply for Output Clock Buffers 2.5V Nominal 2.5V Power Supply for PLL Power Supply for two-line serial Interface Common Ground Analog Ground 2.5V Nominal 2.5V or 3.3V Nominal 0.0V Ground 0.0V Analog Ground Notes: 1. PU= internal pull-up 2. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces Document #: 38-07457 Rev. *A Page 2 of 11 CY2SSTV850 Function Table Inputs AVDD GND GND 2.5V 2.5V Nom 2.5V CLKINT L H L H Design Nom CLKINC H L H L Design Hi-Z Hi-Z Hi-Z Hi-Z Off YT(0:9)[3] L H L H H L H L Outputs YC(0:9)[3] FBOUTT L H L H FBOUTC H L H L PLL BYPASSED/OFF BYPASSED/OFF On On <20 MHz <30 MHZ <20 MHz <30 MHz Power Management The individual output enable/disable control of the CY2SSTV850 allows the user to implement unique power management schemes into the design. Outputs are three-stated when disabled through the two-line interface as individual bits are set low in Byte 0 and Byte 1 registers. The feedback output pair (FBOUTT, FBOUTC) cannot be disabled via two-line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial "runt" clocks. Byte0: Output Register (1 = Enable, 0 = Disable) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 3, 2 5, 6 10, 9 20, 19 22, 23 46, 47 44, 43 39, 40 Description YT0, YC0 YT1, YC1 YT2, YC2 YT3, YC3 YT4, YC4 YT5, YC5 YT6, YC6 YT7, YC7 Zero-delay Buffer When used as a zero-delay buffer the CY2SSTV850 will likely be in a nested clock tree application. For these applications the CY2SSTV850 offers a differential clock input pair as a PLL reference. The CY2SSTV850 then can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBINT, is connected to the feedback output, FBOUTT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. Byte1: Output Register (1 = Enable, 0 = Disable) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 0 0 0 0 0 Pin# 29, 30 27, 26 Description YT8, YC8 YT9, YC9 Reserved Reserved Reserved Reserved Reserved Reserved Serial Control Registers Following the acknowledge of the Address Byte, two additional bytes must be sent: "Command Code" byte, and "Byte Count" byte. 2 Line Serial Interface 2-Line Serial Interface Slave Address A7 1 A6 1 A5 0 A4 1 A3 0 A2 0 A1 1 R/W 0 Writing to the device is accomplished by sequentially sending the device address D2H, the dummy bytes (command code and the number of bytes), and the data bytes. This sequence is illustrated in the following tables. Note: 3. Each output pair can be three-stated via the two-line serial interface. Document #: 38-07457 Rev. *A Page 3 of 11 CY2SSTV850 1 bit Start Bit 7 bits Slave Address 1 bit R/W 1 bit Ack 8 bits Command Code 1 bit Ack 8 bits Byte Count N Ack 1 bit Data Byte 0 8 bits Ack 1 bit Data Byte 1 8 bits Ack 1 bit ..... Byte Byte N 8 bits Ack 1 bit Stop 1 bit Table 1. Timing Requirements for the 2-line Serial Interface over Recommended Ranges of Operating Free-air Temperature and VDDI from 3.3V to 3.5V Parameter fSCLK tBUS tSU(STARt) tH(START) tW(SCLL) tW(SCLH) tR(SDATA) tF(SDATA) tSU(SDATA) tH(SDATA) tSU(STOP) SCLK frequency Bus free time START set-up time START hold time SCLK low pulse duration SCLK high pulse duration SDATA input rise time SDATA input fall time SDATA set-up time SDATA hold time STOP set-up time 250 0 4 4.7 4.7 4.0 4.7 4.0 1000 300 Description Min. Max. 100 Unit kHz s s s s s ns ns ns ns s Document #: 38-07457 Rev. *A Page 4 of 11 CY2SSTV850 Maximum Ratings[4] Input Voltage Relative to VSS:...............................VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................. -65C to +150C Operating Temperature: .................................... 0C to +70C Maximum Power Supply: ................................................3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters[5] (AVDD = VDDQ = 2.5V 5%, VDDI = 3.3V 5%, TA = 0C to +70C) Parameter VIL VIH VID VIX IIN IOL IOH VOL VOH VOUT VOC IOZ IDDQ IDD Description Input Low Voltage Input High Voltage Differential Input Voltage[6] Differential Input Crossing Voltage[7] Input Current Output Low Current Output High Current Output Low Voltage Output High Voltage Output Voltage Swing[8] Output Crossing Voltage[9] High-Impedance Output Current Dynamic Supply Current[10] PLL Supply Current VO = GND or VO = VDDQ All VDDQ and VDDI, FO = 170 MHz AVDD only CLKINT, FBINT CLKTIN, FBINT VIN = 0V or VIN = VDDQ, CLKINT, FBINT VDDQ = 2.375V, VOUT = 1.2V VDDQ = 2.375V, VOUT = 1V VDDQ = 2.375V, IOL = 12 mA VDDQ = 2.375V, IOH = -12 mA 1.7 1.1 (VDDQ/2) - 0.2 -10 235 9 VDDQ/2 VDDQ-0.4 (VDDQ/2) + 0.2 10 300 12 Conditions SDATA, SCLK 2.2 0.35 (VDDQ/2) - 0.2 -10 26 -18 35 -32 0.6 VDDQ/2 VDDQ + 0.6 (VDDQ/2) + 0.2 10 Min. Typ. Max. 1.0 Unit V V V V A mA mA V V V V A mA mA Input Pin Capacitance 2.5 3 3.5 pF Cin Notes: 4. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. Unused inputs must be held HIGH or LOW to prevent them from floating. 6. Differential input signal voltage specifies the differential voltage |VTR - VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 7. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing. 8. For load conditions see Figure 6. 9. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120 resistor. See Figure 6. 10. All outputs switching loaded with 16 pF in 60 environment. See Figure 6. Document #: 38-07457 Rev. *A Page 5 of 11 CY2SSTV850 AC Parameters[11, 12] (VDD = VDDQ = 2.5V5%, VDDI = 3.3V5%, TA = 0C to +70C) Parameter fCLK tDC tlock tR/tF tpZL, tpZH tpLZ, tpHZ tCCJ tjit(h-per) tPLH tPHL tSK(0) tPHASE tJITT(PHASE) td(0) Description Operating Clock Frequency Input Clock Duty Cycle[13] Maximum PLL lock Time Output Clocks Slew Rate Output Enable Time[14] (all outputs) Output Disable Time[14] (all outputs) Cycle to Cycle Jitter Half-period jitter [15] Conditions AVDD, VDD = 2.5V 0.2V Min. 60 40 Typ. Max. 170 60 100 2 Unit MHz % s V/ns ns ns 20% to 80% of VOD 1 3 3 f > 66 MHz f > 66 MHz -100 -100 1.5 1.5 3.5 3.5 100 100 6 6 100 ps ps ns ns ps ps ps ps Low-to-High Propagation Delay, CLKINT to YT[0:9] High-to-Low Propagation Delay, CLKINT to YT[0:9] Any Output to Any Output Skew[16] Phase Error[16] f > 66 MHz CLKIN pins to FBIN pins at the DUT[17] -150 -50 30 150 50 140 Phase Error Jitter Dynamic Phase Offset Note: 11. Parameters are guaranteed by design and characterization. Not 100% tested in production. 12. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down spread of -0.5%. 13. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWH/tC, where the cycle time (tC) decreases as the frequency goes up. 14. Refers to transition of non-inverting output. 15. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. 16. All differential input and output terminals are terminated with 120/16 pF as shown in Figure 6. 17. DUT refers to Device Under Test. Document #: 38-07457 Rev. *A Page 6 of 11 CY2SSTV850 Differential Parameter Measurement Information CLKINT CLKINC FBINT FBINC t()n t()n = t() n+ 1 1=N n N t()n N (is large number of samples) Figure 1. Static Phase Offset CLKINT CLKINC FBINT FBINC td() t() td() td() t( ) td() Figure 2. Dynamic Phase Offset YT[0:9], FBOUTT YC[0:9], FBOUTC YT[0:9], FBOUTT YC[0:9], FBOUTC tsk(o) Figure 3. Output Skew Document #: 38-07457 Rev. *A Page 7 of 11 CY2SSTV850 YT[0:9], FBOUTT YC[0:9], FBOUTC t(hper_n) 1 f(o) t(hper_N+1) tjit(hper) = thper(n) - 1 2x fo Figure 4. Half-Period Jitter YT[0:9], FBOUTT YC[0:9], FBOUTC t c(n) tjit(cc) = tc(n)-tc(n+1) Figure 5. Cycle-to-Cycle Jitter t c(n) VDD VDD V D D /2 16pF C LKT 60 O hm VTR R T = 120 O hm C LKC 60 O hm 16pF V D D /2 VCP R e c e iv e r Figure 6. Differential Signal Using Direct Termination Resistor Document #: 38-07457 Rev. *A Page 8 of 11 CY2SSTV850 Ordering Information Part Number CY2SSTV850OC CY2SSTV850OCT CY2SSTV850ZC CY2SSTV850ZCT Package Type 48-pin SSOP 48-pin SSOP - Tape and Reel 48-pin TSSOP 48-pin TSSOP - Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Package Drawing and Dimensions 48-Lead Shrunk Small Outline Package O48 51-85061-*C Document #: 38-07457 Rev. *A Page 9 of 11 CY2SSTV850 Package Drawing and Dimensions (continued) 48-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48 51-85059-*B Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07457 Rev. *A Page 10 of 11 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2SSTV850 Revision History Document Title: CY2SSTV850 Differential Clock Buffer/Driver Document #: 38-07457 Rev. *A REV. ** *A ECN NO. 117540 122933 Issue Date 09/09/02 12/18/02 Orig. of Change HWT RBI New data sheet Add power up requirements to maximum ratings information Description of Change Document #: 38-07457 Rev. *A Page 11 of 11 |
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